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Large-scale hardware logic emulation using software-configurable hardware provides a new means to rapidly prototype large designs such as advanced microprocessors, thereby significantly improving pre-tape out verification of complex integrated circuits.The essence of hardware logic emulation is the provision of a hardware prototype of the circuit being designed. Such a hardware prototype can execute both pseudo-random verification vectors and software application programs up to six orders-of-magnitude faster than conventional software logic simulators. Trillions of verification vectors can be run on the emulation prototype for verification in only a few weeks compared to the prior best practice of running only billions of verification vectors in many months. The provision of "virtual silicon" for the Motorola's 68060 superscalar microprocessor before tape out facilitated true concurrent engineering, full functional verification of the design, system (hardware/software) integration and debug, resulting in a substantial reduction in cycle time and time to market. Elimination of several silicon re-spins is a significant distinguishing result of emulation verification. Application of hardware logic emulation requires a sound design methodology with an ability to generate a full-chip gate-level model from the HDL models.Development of emulation library, equivalent emulation models for custom blocks, and modeling design memories were some of the interesting challenges encountered in successfully building a reconfigurable prototype for the M68060 microprocessor. Once the prototype is validated to 'functionally' represent the M68060, it is extensively utilized to verify test cards, testers, perform architectural analysis, run benchmarks, conformance tests, run application software in target systems, verify post-silicon bug fixes, and many more tasks which would normally not be possible before fabricating a silicon using conventional technologies. Emulation verification is rapidly becoming a required verification tool to manage the next wave of design complexity.