On automatic generation of RTL validation test benches using circuit testing techniques
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Design Verification by Test Vectors and Arithmetic Transform Universal Test Set
IEEE Transactions on Computers
Software-Based Self-Testing of Embedded Processors
IEEE Transactions on Computers
Journal of Electronic Testing: Theory and Applications
The coupling model for function and delay faults
Journal of Electronic Testing: Theory and Applications
On Built-In Self-Test for Adders
Journal of Electronic Testing: Theory and Applications
Robust Coupling Delay Test Sets
Journal of Electronic Testing: Theory and Applications
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Conventional automatic test-pattern generation (ATPG) cannot effectively handle designs employing blocks whose implementation details are either unknown, unavailable, or subject to change. Realization-independent block testing for cores (RIBTEC), a novel ATPG program for such designs, is described, which employs a functional (behavioral) fault model based on a class of nonexhaustive “universal” test sets. Given a circuit's high-level block structure, RIBTEC constructs a universal test set (UTS) for each block from its functional description in such a way that realization independence of the blocks is ensured. Experimental results are presented for representative datapath circuits, which demonstrate that RIBTEC achieves very high fault coverage and an exceptionally high level of realization independence. We also show that RIBTEC can be applied to designs containing a class of small intellectual property (IP) circuits (cores)