On automatic generation of RTL validation test benches using circuit testing techniques

Authors:
Indradeep Ghosh;Srivaths Ravi
Affiliations:
Fujitsu Laboratories of America, Sunnyvale, CA;NEC Laboratories America, Princeton, NJ
Venue:
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Year:
2003

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Abstract

In this paper, we examine how good validation test benches can be automatically generated starting from the RTL description of a circuit. We develop our methodology based on extensive experiments performed with several popular benchmarks as well as industrial circuits.