On automatic generation of RTL validation test benches using circuit testing techniques
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Validation Vector Grade (VVG): A New Coverage Metric for Validation and Test
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
REGISTER-TRANSFER LEVEL FAULT MODELING AND TEST EVALUATION TECHNIQUES FOR VLSI CIRCUITS
ITC '00 Proceedings of the 2000 IEEE International Test Conference
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RTL-based on high level design methodology suffers a major drawback in the area of testability analysis due to lack of effective RTL fault model. Testability of a design is considered structure dependent. Since the structure of a design changes drastically with every logic synthesis run, testability analysis is performed only after final logic synthesis and therefore findings of such effort are too late to be implemented in the design without a significant schedule impact. In this paper, we analyze the testability relationship between the RT level design and different structural (gate level) implementations resulting from optimization driven logic synthesis runs. We empirically establish that the testability properties of structural implementations are derived from architectural descriptions at the RT level and therefore logic synthesis does not significantly impact them. Furthermore, various different structural implementations resulting from logic synthesis (with different optimization constraints) exhibit poor testability in the same RTL design space. The data presented in this paper provides a missing key ingredient towards successful RTL fault modeling. We also propose the use of preliminary gate level netlist for early analysis to estimate testability properties of the final implementation.