Fault-tolerant quantum computation with constant error
STOC '97 Proceedings of the twenty-ninth annual ACM symposium on Theory of computing
Explorations in quantum computing
Explorations in quantum computing
A Minimal Universal Test Set for Self-Test of EXOR-Sum-of-Products Circuits
IEEE Transactions on Computers
Quantum computation and quantum information
Quantum computation and quantum information
Stuck-Fault Tests vs. Actual Defects
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Fault-tolerant quantum computation
FOCS '96 Proceedings of the 37th Annual Symposium on Foundations of Computer Science
Testing for Missing-Gate Faults in Reversible Circuits
ATS '04 Proceedings of the 13th Asian Test Symposium
Quantum Circuit Simplification Using Templates
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Test Generation and Fault Localization for Quantum Circuits
ISMVL '05 Proceedings of the 35th International Symposium on Multiple-Valued Logic
Nano, quantum, and molecular computing: are we ready for the validation and test challenges?
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
Automatic fault detection in combinational switching networks
FOCS '61 Proceedings of the 2nd Annual Symposium on Switching Circuit Theory and Logical Design (SWCT 1961)
Testing for faults in combinational cellular logic arrays
FOCS '67 Proceedings of the 8th Annual Symposium on Switching and Automata Theory (SWAT 1967)
Book review on quantum computation and quantum information
Quantum Information & Computation
Graph-based simulation of quantum computation in the density matrix representation
Quantum Information & Computation
Fault testing for reversible circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fault diagnosis in reversible circuits under missing-gate fault model
Computers and Electrical Engineering
| Hi-index | 0.01 |
In classical test and verification one develops a test set separating a correct circuit from a circuit containing any considered fault. Classical faults are modelled at the logical level by fault models that act on classical states. The stuck fault model, thought of as a lead connected to a power rail or to a ground, is most typically considered. A classical test set complete for the stuck fault model propagates both binary basis states, 0 and 1, through all nodes in a network and is known to detect many physical faults. A classical test set complete for the stuck fault model allows all circuit nodes to be completely tested and verifies the function of many gates. It is natural to ask if one may adapt any of the known classical methods to test quantum circuits. Of course, classical fault models do not capture all the logical failures found in quantum circuits. The first obstacle faced when using methods from classical test is developing a set of realistic quantum-logical fault models (a question which we address, but will likely remain largely open until the advent of the first quantum computer). Developing fault models to abstract the test problem away from the device level motivated our study. Several results are established. First, we describe typical modes of failure present in the physical design of quantum circuits. From this we develop fault models for quantum binary quantum circuits that enable testing at the logical level. The application of these fault models is shown by adapting the classical test set generation technique known as constructing a fault table to generate quantum test sets. A test set developed using this method will detect each of the considered faults.