Generalized Partially-Mixed-Polarity Reed-Muller Expansion and Its Fast Computation

Authors:
Haomin Wu;M. A. Perkowski;Xiaoqiang Zeng;Nan Zhuang
Affiliations:
-;-;-;-
Venue:
IEEE Transactions on Computers
Year:
1996

Citing 5
Cited 3

On the Complexity of Mod-2l Sum PLA's

IEEE Transactions on Computers
Fast exact and quasi-minimal minimization of highly testable fixed-polarity AND/XOR canonical networks

DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Boolean Matrix Transforms for the Minimization of Modulo-2 Canonical Expansions

IEEE Transactions on Computers
Logic Synthesis and Optimization

Logic Synthesis and Optimization
Logic Minimization Algorithms for VLSI Synthesis

Logic Minimization Algorithms for VLSI Synthesis

Testable design of GRM network with EXOR-tree for detecting stuck-at and bridging faults

Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Bridging fault detection in Double Fixed-Polarity Reed-Muller (DFPRM) PLA

Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Testable design of AND-EXOR logic networks with universal test sets

Computers and Electrical Engineering

Quantified Score

Hi-index	14.98

Visualization

Abstract

Generalized Partially-Mixed-Polarity Reed-Muller (GPMPRM) expansion, a canonical subfamily of Exclusive Sum of Products (ESOP), is presented. An efficient algorithm in two-dimensional data flow is proposed for computation of the GPMPRM forms. MCNC benchmark experimental results show that the minimal GPMPRM forms of these functions, on the average, have similar number of terms to their Sum of Products (SOP) counterparts while there are many functions for which the GPMPRM circuits are much smaller.