A parallel version of the Itoh-Tsujii multiplicative inversion algorithm

Authors:
Francisco Rodríguez-Henríquez;Guillermo Morales-Luna;Nazar A. Saqib;Nareli Cruz-Cortés
Affiliations:
Computer Science Department, Centro de Investigación y de Estudios Avanzados del IPN, México D.F.;Computer Science Department, Centro de Investigación y de Estudios Avanzados del IPN, México D.F.;Centre for Cyber Technology and Spectrum Management, NUST, Islamabad, Pakistan;Computer Science Department, Centro de Investigación y de Estudios Avanzados del IPN, México D.F.
Venue:
ARC'07 Proceedings of the 3rd international conference on Reconfigurable computing: architectures, tools and applications
Year:
2007

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Abstract

In this contribution, we derive a novel parallel formulation of the standard Itoh-Tsujii algorithm for multiplicative inverse computation over GF(2m). When implemented in a Virtex 3200E FPGA device, our design is able to compute multiplicative inversion over GF(2193) after 20 clock cycles in about 0.94µS.