Efficient FPGA-based karatsuba multipliers for polynomials over F2

Authors:
Joachim von zur Gathen;Jamshid Shokrollahi
Affiliations:
B-IT, Universität Bonn, Bonn, Germany;B-IT, Universität Bonn, Bonn, Germany
Venue:
SAC'05 Proceedings of the 12th international conference on Selected Areas in Cryptography
Year:
2005

Citing 7
Cited 7

On arithmetical algorithms over finite fields

Journal of Combinatorial Theory Series A
Arithmetic and factorization of polynomial over F2 (extended abstract)

ISSAC '96 Proceedings of the 1996 international symposium on Symbolic and algebraic computation
Fast Algorithms for Digital Signal Processing

Fast Algorithms for Digital Signal Processing
Optimal Extension Fields for Fast Arithmetic in Public-Key Algorithms

CRYPTO '98 Proceedings of the 18th Annual International Cryptology Conference on Advances in Cryptology
Guide to Elliptic Curve Cryptography

Guide to Elliptic Curve Cryptography
Modern Computer Algebra

Modern Computer Algebra
Polynomial and Normal Bases for Finite Fields

Journal of Cryptology

A New Approach to Subquadratic Space Complexity Parallel Multipliers for Extended Binary Fields

IEEE Transactions on Computers
High-speed hardware implementations of Elliptic Curve Cryptography: A survey

Journal of Systems Architecture: the EUROMICRO Journal
Efficient Multiplication Using Type 2 Optimal Normal Bases

WAIFI '07 Proceedings of the 1st international workshop on Arithmetic of Finite Fields
Explicit formulas for efficient multiplication in F36m

SAC'07 Proceedings of the 14th international conference on Selected areas in cryptography
Complexity analysis and efficient implementations of bit parallel finite field multipliers based on Karatsuba-Ofman algorithm on FPGAs

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Combining multiplication methods with optimized processing sequence for polynomial multiplier in GF(2k)

WEWoRC'11 Proceedings of the 4th Western European conference on Research in Cryptology
Towards efficient arithmetic for lattice-based cryptography on reconfigurable hardware

LATINCRYPT'12 Proceedings of the 2nd international conference on Cryptology and Information Security in Latin America

Quantified Score

Hi-index	0.00

Visualization

Abstract

We study different possibilities of implementing the Karatsuba multiplier for polynomials over ${\mathbb F}_{2}$ on FPGAs. This is a core task for implementing finite fields of characteristic 2. Algorithmic and platform dependent optimizations yield efficient hardware designs. The resulting structure is hybrid in two different aspects. On the one hand, a combination of the classical and the Karatsuba methods decreases the number of bit operations. On the other hand, a mixture of sequential and combinational circuit design techniques includes pipelining and can be adapted flexibly to time-area constraints. The approach—both theory and implementation—can be viewed as a further step towards taming the machinery of fast algorithmics for hardware applications.