The Art of Electronics
A Generalized Method for Constructing Subquadratic Complexity GF(2^k) Multipliers
IEEE Transactions on Computers
Five, Six, and Seven-Term Karatsuba-Like Formulae
IEEE Transactions on Computers
Proceedings of the conference on Design, Automation and Test in Europe - Volume 3
Comments on "Five, Six, and Seven-Term Karatsuba-Like Formulae"
IEEE Transactions on Computers
An efficient polynomial multiplier in GF(2m) and its application to ECC designs
Proceedings of the conference on Design, automation and test in Europe
Polynomial Multiplication over Finite Fields Using Field Extensions and Interpolation
ARITH '09 Proceedings of the 2009 19th IEEE Symposium on Computer Arithmetic
Improved n-Term Karatsuba-Like Formulas in GF(2)
IEEE Transactions on Computers
Efficient FPGA-based karatsuba multipliers for polynomials over F2
SAC'05 Proceedings of the 12th international conference on Selected Areas in Cryptography
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In this paper we present an approach for optimizing the implementation of hardware multipliers in GF(2k). We investigate two different strategies namely the reduction of the complexity of the multiplication methods and the combination of different multiplication methods as a means to reduce the area and/or energy consumption of the hardware multiplier. As a means to explore the design space concerning the segmentation of the operands and the selection of the most appropriate multiplication methods we introduce an algorithm which determines the best combination of the multiplication methods. In order to assess the validity of our approach we have benchmarked it against theoretical results reconstructed from literature and against synthesis results using our inhouse 130 nm technology. The former revealed that our designs are up to 32 per cent smaller than those given in literature, the latter showed that our area prediction is extremely accurate.