Low complexity bit-parallel multipliers based on a class of irreducible pentanomials

Authors:
José Luis Imaña;Romá Hermida;Francisco Tirado
Affiliations:
Department of Computer Architecture and Systems Engineering, Complutense University, Madrid, Spain;Department of Computer Architecture and Systems Engineering, Complutense University, Madrid, Spain;Department of Computer Architecture and Systems Engineering, Complutense University, Madrid, Spain
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2006

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Abstract

In this paper, we consider the design of bit-parallel canonical basis multipliers over the finite field GF(2m) generated by a special type of irreducible pentanomial that is used as an irreducible polynomial in the Advanced Encryption Standard (AES). Explicit formulas for the coordinates of the multiplier are given. The main advantage of our design is that some of the expressions obtained are common to any irreducible polynomial, so our multiplier can be generalized to perform the multiplication over general irreducible polynomials. Moreover, the obtained expressions can be easily converted to parameterizable code using hardware description languages. The theoretical complexity analysis also shows that our bit-parallel multipliers present a reduced number of XOR gates with respect to the best known results found in the literature.