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IEEE Transactions on Computers
Parallel Multipliers Based on Special Irreducible Pentanomials
IEEE Transactions on Computers
IEEE Transactions on Computers
Low complexity bit parallel multiplier for GF (2m) generated by equally-spaced trinomials
Information Processing Letters
Low complexity bit-parallel multipliers based on a class of irreducible pentanomials
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Speedup of bit-parallel Karatsuba multiplier in GF(2 m) generated by trinomials
Information Processing Letters
Explicit formulae of polynomial basis squarer for pentanomials using weakly dual basis
Integration, the VLSI Journal
Low complexity bit parallel architectures for polynomial basis multiplication over GF(2m)
IEEE Transactions on Computers
Integration, the VLSI Journal
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We present a bit-parallel polynomial basis multiplier based on a new divide-and-conquer approach using squaring. In particular, we apply the proposed approach to special types of irreducible pentanomials called as types I and II pentanomials, and induce explicit formulae and complexities of the proposed multiplier for these types of pentanomials. As a result, the proposed multiplier for type I pentanomials has almost the same time complexity, but about 25% reduced space complexity compared with the best known results in the literature. For type II pentanomials, we obtain the multiplier which has the lowest time complexity and about 25% reduced space complexity than the best known polynomial basis multipliers.