Speedup of bit-parallel Karatsuba multiplier in GF(2 m) generated by trinomials

Authors:
Yin Li;Gong-liang Chen;Jian-hua Li
Affiliations:
School of Information Security Engineering, Shanghai Jiaotong University, Shanghai 200240, China;School of Information Security Engineering, Shanghai Jiaotong University, Shanghai 200240, China;School of Information Security Engineering, Shanghai Jiaotong University, Shanghai 200240, China and Department of Electronic Engineering, Shanghai Jiaotong University, Shanghai 200240, China
Venue:
Information Processing Letters
Year:
2011

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Abstract

In this letter, we present a speedup of bit-parallel Karatsuba multiplier in GF(2^m) generated with a class of irreducible trinomials. Applying a slightly modified Karatsuba approach, we can save one XOR gate delay at the cost of little increase of space complexity. The proposed multiplier has a lower time complexity than the previous Karatsuba multipliers except for those based on equal-space trinomial or all-one polynomial. In counterpart it only requires one more XOR time delay than the best known multipliers for trinomials but maintains a smaller number of logic gates.