Low complexity bit parallel multiplier for GF (2m) generated by equally-spaced trinomials

Authors:
Haibin Shen;Yier Jin
Affiliations:
Institute of VLSI Design, Zhejiang University, Hangzhou, China;Institute of VLSI Design, Zhejiang University, Hangzhou, China and Department of Electrical Engineering, Yale University, 10 Hillhouse Avenue, New Haven, CT 06520, USA
Venue:
Information Processing Letters
Year:
2008

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Abstract

Based on the shifted polynomial basis (SPB), a high efficient bit-parallel multiplier for the field GF(2^m) defined by an equally-spaced trinomial (EST) is proposed. The use of SPB significantly reduces time delay of the proposed multiplier and at the same time Karatsuba method is combined with SPB to decrease space complexity. As a result, with the same time complexity, approximately 3/4 gates of previous multipliers are used in the proposed multiplier.