A Comparison of VLSI Architecture of Finite Field Multipliers Using Dual, Normal, or Standard Bases
IEEE Transactions on Computers
Structure of parallel multipliers for a class of fields GF(2m)
Information and Computation
An Algorithm to Design Finite Field Multipliers Using a Self-Dual Normal Basis
IEEE Transactions on Computers
Bit serial multiplication in finite fields
SIAM Journal on Discrete Mathematics
IEEE Transactions on Computers - Special issue on computer arithmetic
Designs, Codes and Cryptography
Constructive problems for irreducible polynomials over finite fields
Proceedings of the third Canadian workshop on Information theory and applications
Low Complexity Bit-Parallel Multipliers for a Class of Finite Fields
IEEE Transactions on Computers
A Modified Massey-Omura Parallel Multiplier for a Class of Finite Fields
IEEE Transactions on Computers
GF(2m) Multiplication and Division Over the Dual Basis
IEEE Transactions on Computers
IEEE Transactions on Computers
Efficient exponentiation using weakly dual basis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
A New Construction of Massey-Omura Parallel Multiplier over GF(2^{m})
IEEE Transactions on Computers
Montgomery Multiplier and Squarer for a Class of Finite Fields
IEEE Transactions on Computers
Montgomery Multiplier and Squarer in GF(2m)
CHES '00 Proceedings of the Second International Workshop on Cryptographic Hardware and Embedded Systems
Hardware architectures for public key cryptography
Integration, the VLSI Journal
Parallel Multipliers Based on Special Irreducible Pentanomials
IEEE Transactions on Computers
Synthesis of integer multipliers in sum of pseudoproducts form
Integration, the VLSI Journal
Fast Bit-Parallel GF(2^n) Multiplier for All Trinomials
IEEE Transactions on Computers
Ringed bit-parallel systolic multipliers over a class of fields GF(2m)
Integration, the VLSI Journal
Concurrent Error Detection in a Polynomial Basis Multiplier over GF(2m)
Journal of Electronic Testing: Theory and Applications
A New Approach to Subquadratic Space Complexity Parallel Multipliers for Extended Binary Fields
IEEE Transactions on Computers
Low complexity bit parallel multiplier for GF (2m) generated by equally-spaced trinomials
Information Processing Letters
Digit-Serial Structures for the Shifted Polynomial Basis Multiplication over Binary Extension Fields
WAIFI '08 Proceedings of the 2nd international workshop on Arithmetic of Finite Fields
Computers and Electrical Engineering
Scalable and Systolic Montgomery Multipliers over GF(2m)
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Unified parallel systolic multiplier over GF(2m)
Journal of Computer Science and Technology
Low-complexity bit-parallel dual basis multipliers using the modified Booth's algorithm
Computers and Electrical Engineering
Ringed bit-parallel systolic multipliers over a class of fields GF(2m)
Integration, the VLSI Journal
Information Processing Letters
ICCSA'05 Proceedings of the 2005 international conference on Computational Science and its Applications - Volume Part I
ICISC'05 Proceedings of the 8th international conference on Information Security and Cryptology
New bit parallel multiplier with low space complexity for all irreducible trinomials over GF(2n)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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New structures of bit-parallel weakly dual basis (WDB) multipliers over the binary ground field are proposed. An upper bound on the size complexity of bit-parallel multiplier using an arbitrary generating polynomial is given. When the generating polynomial is an irreducible trinomial xm + xk + 1, $1\le k\le \left\lfloor {{{m \over 2}}} \right\rfloor,$ the structure of the proposed bit-parallel multiplier requires only m2 two-input AND gates and at most m2$-$1 XOR gates. The time delay is no greater than $T_A + (\lceil \log_2 m\rceil + 2)T_X,$ where TA and TX are the time delays of an AND gate and an XOR gate, respectively.