Multiplexer implementation of low-complexity polynomial basis multiplier in GF(2m) using all one polynomial

Authors:
Che Wun Chiou;Chiou-Yng Lee;Yun-Chi Yeh
Affiliations:
Department of Computer Science & Information Engineering, Ching Yun University, 229, Chien-Hsin Rd., Chung-Li 320, Taiwan, ROC;Department of Computer Information and Network Engineering, Lunghwa University of Science and Technology, Taoyuan County 333, Taiwan, ROC;Department of Electronic Engineering, Ching Yun University, Jhong-Li 320, Taiwan, ROC
Venue:
Information Processing Letters
Year:
2011

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Abstract

Polynomial basis multipliers are realized by conventional AND and XOR gates. In this study, polynomial basis multiplier is implemented by multiplexers rather than traditional AND and XOR gates. Two bits are processed at the same time. The proposed multiplexer-based multiplier saves about 14% space complexity as compared to other existing multipliers. Furthermore, the proposed multiplier also saves about 37% time complexity (for example, m=156) while comparing with other existing multipliers.