VLSI Architectures for Computing Multiplications and Inverses in GF(2m)
IEEE Transactions on Computers
Introduction to finite fields and their applications
Introduction to finite fields and their applications
A Comparison of VLSI Architecture of Finite Field Multipliers Using Dual, Normal, or Standard Bases
IEEE Transactions on Computers
Optimal normal bases in GF(pn)
Discrete Applied Mathematics
Structure of parallel multipliers for a class of fields GF(2m)
Information and Computation
Discrete Applied Mathematics
IEEE Transactions on Computers - Special issue on computer arithmetic
Designs, Codes and Cryptography
Efficient Exponentiation of a Primitive Root in GF(2m)
IEEE Transactions on Computers
Efficient Multiplier Architectures for Galois Fields GF(24n)
IEEE Transactions on Computers
Low-Complexity Bit-Parallel Canonical and Normal Basis Multipliers for a Class of Finite Fields
IEEE Transactions on Computers
Low Complexity Bit-Parallel Multipliers for a Class of Finite Fields
IEEE Transactions on Computers
Systolic Array Implementation of Euclid's Algorithm for Inversion and Division in GF (2m)
IEEE Transactions on Computers
IEEE Transactions on Computers
Mastrovito Multiplier for All Trinomials
IEEE Transactions on Computers
New Low-Complexity Bit-Parallel Finite Field Multipliers Using Weakly Dual Bases
IEEE Transactions on Computers
Mastrovito Multiplier for General Irreducible Polynomials
IEEE Transactions on Computers
A Modified Massey-Omura Parallel Multiplier for a Class of Finite Fields
IEEE Transactions on Computers
GF(2m) Multiplication and Division Over the Dual Basis
IEEE Transactions on Computers
IEEE Transactions on Computers
VLSI Designs for Multiplication over Finite Fields GF (2m)
AAECC-6 Proceedings of the 6th International Conference, on Applied Algebra, Algebraic Algorithms and Error-Correcting Codes
Efficient Multiplication Beyond Optimal Normal Bases
IEEE Transactions on Computers
Hardware architectures for public key cryptography
Integration, the VLSI Journal
Fast Normal Basis Multiplication Using General Purpose Processors
IEEE Transactions on Computers
Efficient digit-serial normal basis multipliers over binary extension fields
ACM Transactions on Embedded Computing Systems (TECS)
Low Complexity Word-Level Sequential Normal Basis Multipliers
IEEE Transactions on Computers
Hardware and Software Normal Basis Arithmetic for Pairing-Based Cryptography in Characteristic Three
IEEE Transactions on Computers
IEEE Transactions on Computers
Efficient Algorithms and Architectures for Field Multiplication Using Gaussian Normal Bases
IEEE Transactions on Computers
Concurrent Error Detection in a Polynomial Basis Multiplier over GF(2m)
Journal of Electronic Testing: Theory and Applications
A New Approach to Subquadratic Space Complexity Parallel Multipliers for Extended Binary Fields
IEEE Transactions on Computers
A Novel Architecture for Galois Fields GF(2^m) Multipliers Based on Mastrovito Scheme
IEEE Transactions on Computers
WG: A family of stream ciphers with designed randomness properties
Information Sciences: an International Journal
On complexity of normal basis multiplier using modified Booth's algorithm
AIC'07 Proceedings of the 7th Conference on 7th WSEAS International Conference on Applied Informatics and Communications - Volume 7
On complexity of normal basis multiplier using modified Booth's algorithm
AIC'07 Proceedings of the 7th Conference on 7th WSEAS International Conference on Applied Informatics and Communications - Volume 7
Low complexity bit parallel multiplier for GF (2m) generated by equally-spaced trinomials
Information Processing Letters
A New Parallel Multiplier for Type II Optimal Normal Basis
Computational Intelligence and Security
Efficient Multiplication Using Type 2 Optimal Normal Bases
WAIFI '07 Proceedings of the 1st international workshop on Arithmetic of Finite Fields
Low-complexity bit-parallel dual basis multipliers using the modified Booth's algorithm
Computers and Electrical Engineering
Concurrent error detection architectures for Gaussian normal basis multiplication over GF(2m)
Integration, the VLSI Journal
Journal of Signal Processing Systems
A high-speed word level finite field multiplier in F2m using redundant representation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An extension of TYT inversion algorithm in polynomial basis
Information Processing Letters
Construct public key encryption scheme using ergodic matrices over GF(2)
TAMC'07 Proceedings of the 4th international conference on Theory and applications of models of computation
A modified low complexity digit-level Gaussian normal basis multiplier
WAIFI'10 Proceedings of the Third international conference on Arithmetic of finite fields
Information Processing Letters
Modified sequential normal basis multipliers for type II optimal normal bases
ICCSA'05 Proceedings of the 2005 international conference on Computational Science and Its Applications - Volume Part II
Modified serial multipliers for Type-IV gaussian normal bases
INDOCRYPT'05 Proceedings of the 6th international conference on Cryptology in India
Concurrent error detection architectures for field multiplication using gaussian normal basis
ISPEC'10 Proceedings of the 6th international conference on Information Security Practice and Experience
Information Processing Letters
Hi-index | 15.01 |
The Massey-Omura multiplier of GF(2^{m}) uses a normal basis and its bit parallel version is usually implemented using m identical combinational logic blocks whose inputs are cyclically shifted from one another. In the past, it was shown that, for a class of finite fields defined by irreducible all-one polynomials, the parallel Massey-Omura multiplier had redundancy and a modified architecture of lower circuit complexity was proposed. In this article, it is shown that, not only does this type of multipliers contain redundancy in that special class of finite fields, but it also has redundancy in fields GF(2^{m}) defined by any irreducible polynomial. By removing the redundancy, we propose a new architecture for the normal basis parallel multiplier, which is applicable to any arbitrary finite field and has significantly lower circuit complexity compared to the original Massey-Omura normal basis parallel multiplier. The proposed multiplier structure is also modular and, hence, suitable for VLSI realization. When applied to fields defined by the irreducible all-one polynomials, the multiplier's circuit complexity matches the best result available in the open literature.