VLSI Architectures for Computing Multiplications and Inverses in GF(2m)
IEEE Transactions on Computers
Introduction to finite fields and their applications
Introduction to finite fields and their applications
Use of elliptic curves in cryptography
Lecture notes in computer sciences; 218 on Advances in cryptology---CRYPTO 85
Optimal normal bases in GF(pn)
Discrete Applied Mathematics
Discrete Applied Mathematics
Designs, Codes and Cryptography
An Efficient Optimal Normal Basis Type II Multiplier
IEEE Transactions on Computers
A New Construction of Massey-Omura Parallel Multiplier over GF(2^{m})
IEEE Transactions on Computers
Efficient Algorithms and Architectures for Field Multiplication Using Gaussian Normal Bases
IEEE Transactions on Computers
IEEE Transactions on Computers
FPGA implementation of high performance elliptic curve cryptographic processor over GF(2163)
Journal of Systems Architecture: the EUROMICRO Journal
Efficient Multiplication Using Type 2 Optimal Normal Bases
WAIFI '07 Proceedings of the 1st international workshop on Arithmetic of Finite Fields
Complexity Reduction of Constant Matrix Computations over the Binary Field
WAIFI '07 Proceedings of the 1st international workshop on Arithmetic of Finite Fields
Provably Sublinear Point Multiplication on Koblitz Curves and Its Hardware Implementation
IEEE Transactions on Computers
On parallelization of high-speed processors for elliptic curve cryptography
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Gaussian normal bases have been included in a number of standards, such as IEEE [1] and NIST [2] for elliptic curve digital signature algorithm (ECDSA). Among different finite field operations used in this algorithm, multiplication is the main operation. In this paper, we consider type T Gaussian normal basis (GNB) multipliers over GF(2m), where m is odd. Such fields include five binary fields recommended by NIST for ECDSA. A modified digit-level GNB multiplier over GF(2m) is proposed in this paper. For T 2, a complexity reduction algorithm is proposed to reduce the number of XOR gates without increasing the gate delay of the digit-level multiplier. The original and modified digit-level GNB multipliers are implemented on the Xilinx® Virtex5™ FPGA family for different digit sizes. It is shown that the modified digit-level GNB multiplier requires lower space complexity with almost the same delay as compared to the original type T, T 2, GNB multiplier. Moreover, the bit-parallel GNB multiplier obtained from the proposed modified digit-level multiplier has the least space and time complexities among the existing fast bit-parallel type T GNB multipliers for T 2.