IEEE Transactions on Computers - Special issue on computer arithmetic
Low-Complexity Bit-Parallel Canonical and Normal Basis Multipliers for a Class of Finite Fields
IEEE Transactions on Computers
Low Complexity Bit-Parallel Multipliers for a Class of Finite Fields
IEEE Transactions on Computers
Mastrovito Multiplier for All Trinomials
IEEE Transactions on Computers
Hardware/software codesign of finite field datapath for low-energy Reed-Solomon codecs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Mastrovito Multiplier for General Irreducible Polynomials
IEEE Transactions on Computers
IEEE Transactions on Computers
High-speed architectures for Reed-Solomon decoders
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Elliptic Curve Public Key Cryptosystems
Elliptic Curve Public Key Cryptosystems
A New Construction of Massey-Omura Parallel Multiplier over GF(2^{m})
IEEE Transactions on Computers
GF(2m) Multiplication and Division Over the Dual Basis
IEEE Transactions on Computers
Parallel Multipliers Based on Special Irreducible Pentanomials
IEEE Transactions on Computers
A Generalized Method for Constructing Subquadratic Complexity GF(2^k) Multipliers
IEEE Transactions on Computers
Five, Six, and Seven-Term Karatsuba-Like Formulae
IEEE Transactions on Computers
Fast Bit-Parallel GF(2^n) Multiplier for All Trinomials
IEEE Transactions on Computers
IEEE Transactions on Computers
Efficient Algorithms and Architectures for Field Multiplication Using Gaussian Normal Bases
IEEE Transactions on Computers
Efficient semisystolic architectures for finite-field arithmetic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low complexity bit parallel architectures for polynomial basis multiplication over GF(2m)
IEEE Transactions on Computers
Parallel GF(3m) multiplier for trinomials
Information Processing Letters
New bit parallel multiplier with low space complexity for all irreducible trinomials over GF(2n)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 14.98 |
In the paper a new GF(2^m) multiplier for standard basis representation is developed. Proposed multiplier implements the Mastrovito multiplication scheme and can be designed for every field GF(2^m). A minimum area implementation of the first block of Mastrovito multiplier and a high-speed delay-driven tree architecture for the second block of Mastrovito multiplier are employed in the new circuit. Multiplier complexity and delay are analytically evaluated for many polynomial classes. Timing and area occupation performances of the proposed multiplier are also calculated for many fields used in Reed-Solomon codes applications and compared with those of previously proposed solutions. The comparison shows that the proposed multiplier outperforms previous architectures for every considered GF(2^m) field. The effectiveness of the proposed solution in a real application is verified by implementing in a 0.25ìm CMOS technology the key equation solving block of a (255,239) Reed-Solomon decoder. The use of the proposed multiplier in this application results in a substantial speed improvement without any penalty in silicon area occupation.