VLSI Architectures for Computing Multiplications and Inverses in GF(2m)
IEEE Transactions on Computers
Introduction to finite fields and their applications
Introduction to finite fields and their applications
Optimal normal bases in GF(pn)
Discrete Applied Mathematics
Low-Complexity Bit-Parallel Canonical and Normal Basis Multipliers for a Class of Finite Fields
IEEE Transactions on Computers
An Efficient Optimal Normal Basis Type II Multiplier
IEEE Transactions on Computers
On the Inherent Space Complexity of Fast Parallel Multipliers for GF(2/supm/)
IEEE Transactions on Computers
A New Construction of Massey-Omura Parallel Multiplier over GF(2^{m})
IEEE Transactions on Computers
A Modified Massey-Omura Parallel Multiplier for a Class of Finite Fields
IEEE Transactions on Computers
Efficient Multiplication Beyond Optimal Normal Bases
IEEE Transactions on Computers
Low Complexity Word-Level Sequential Normal Basis Multipliers
IEEE Transactions on Computers
Efficient Algorithms and Architectures for Field Multiplication Using Gaussian Normal Bases
IEEE Transactions on Computers
WG: A family of stream ciphers with designed randomness properties
Information Sciences: an International Journal
Concurrent error detection architectures for Gaussian normal basis multiplication over GF(2m)
Integration, the VLSI Journal
Modified sequential normal basis multipliers for type II optimal normal bases
ICCSA'05 Proceedings of the 2005 international conference on Computational Science and Its Applications - Volume Part II
Modified serial multipliers for Type-IV gaussian normal bases
INDOCRYPT'05 Proceedings of the 6th international conference on Cryptology in India
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In this article, two digit-serial architectures for normal basis multipliers over (GF(2m)) are presented. These two structures have the same gate count and gate delay. We also consider two special cases of optimal normal bases for the two digit-serial architectures. A straightforward implementation leaves gate redundancy in both of them. An algorithm that can considerably reduce the redundancy is also developed. The proposed architectures are compared with the existing ones in terms of gate and time complexities.