Low Complexity Word-Level Sequential Normal Basis Multipliers

• Authors: Arash Reyhani-Masoleh;M. Anwar Hasan
• Venue: IEEE Transactions on Computers
• Year: 2005

For efficient hardware implementation of finite field arithmetic units, the use of a normal basis is advantageous. In this paper, two classes of architectures for multipliers over the finite fieldGF(2^{m}) are proposed. These multipliers are of sequential type, i.e., after receiving the coordinates of the two input field elements, they go throughk, 1\leq k\leq m, iterations (i.e., clock cycles) to finally yield all the coordinates of the product in parallel. The value ofk depends on the word sizew=\left\lceil {\frac{m}{k}}\right\rceil. Forw1, these multipliers are highly area efficient and require fewer number of logic gates even when compared with the most area efficient multipliers available in the open literature. This makes the proposed multipliers suitable for applications where the value ofm is large but space is of concern, e.g., resource constrained cryptographic systems. Additionally, if the field dimensionm is composite, i.e.,m=kn, then the extension of one class of the architectures yields a highly efficient multiplier over composite fields.