VLSI Architectures for Computing Multiplications and Inverses in GF(2m)
IEEE Transactions on Computers
Introduction to finite fields and their applications
Introduction to finite fields and their applications
On orders of optimal normal basis generators
Mathematics of Computation
IEEE Transactions on Computers
Finite Field Multiplier Using Redundant Representation
IEEE Transactions on Computers
Low Complexity Multiplication in a Finite Field Using Ring Representation
IEEE Transactions on Computers
Efficient Multiplication Beyond Optimal Normal Bases
IEEE Transactions on Computers
Guide to Elliptic Curve Cryptography
Guide to Elliptic Curve Cryptography
Low Complexity Word-Level Sequential Normal Basis Multipliers
IEEE Transactions on Computers
A high-speed word level finite field multiplier in F2m using redundant representation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Novel algebraic structure for cyclic codes
AAECC'07 Proceedings of the 17th international conference on Applied algebra, algebraic algorithms and error-correcting codes
An Efficient Finite Field Multiplier Using Redundant Representation
ACM Transactions on Embedded Computing Systems (TECS)
Hi-index | 14.98 |
Two high-speed bit-serial word-parallel or comb-style finite field multipliers are proposed in this paper. The first proposal utilizes a redundant representation for any binary field and the other uses a reordered normal basis for the binary field where a type-II optimal normal basis exists. The proposed redundant representation architecture has a smaller critical path delay compared to the previous methods while the complexities remain about the same. The proposed reordered normal basis multiplier has a significantly smaller critical path delay compared to the previous methods using the same basis or normal basis. Field-programmable gate array (FPGA) implementation results of the proposed multipliers are compared to those of the previous methods using the same basis, which confirms that the proposed multipliers allow a much higher clock rate.