Optimal normal bases in GF(pn)
Discrete Applied Mathematics
IEEE Transactions on Computers
Handbook of Applied Cryptography
Handbook of Applied Cryptography
CMOS Logic Circuit Design
Architecture For A Low Complexity Rate-Adaptive Reed-Solomon Encoder
IEEE Transactions on Computers
Finite Field Multiplier Using Redundant Representation
IEEE Transactions on Computers
VLSI Designs for Multiplication over Finite Fields GF (2m)
AAECC-6 Proceedings of the 6th International Conference, on Applied Algebra, Algebraic Algorithms and Error-Correcting Codes
Fast Multiplication in Finite Fields GF(2N)
CHES '99 Proceedings of the First International Workshop on Cryptographic Hardware and Embedded Systems
Efficient Multiplication Beyond Optimal Normal Bases
IEEE Transactions on Computers
Low Complexity Word-Level Sequential Normal Basis Multipliers
IEEE Transactions on Computers
Comb Architectures for Finite Field Multiplication in F(2^m)
IEEE Transactions on Computers
A New Finite-Field Multiplier Using Redundant Representation
IEEE Transactions on Computers
An implementation of elliptic curve cryptosystems over F2155
IEEE Journal on Selected Areas in Communications
Information Processing Letters
Hi-index | 0.00 |
An efficient word-level finite field multiplier using redundant representation is proposed. The proposed multiplier has a significantly higher speed, compared to previously proposed word-level architectures using either redundant representation or optimal normal basis type I, at the expense of moderately higher area complexity. Furthermore, the new design out-performs other similar proposals when considering the product of area and delay as a measure of performance. ASIC Realization of the proposed design using TSMC’s .18 um CMOS technology for the binary field size of 163 is also presented.