Introduction to finite fields and their applications
Introduction to finite fields and their applications
Optimal normal bases in GF(pn)
Discrete Applied Mathematics
Designs, Codes and Cryptography
On orders of optimal normal basis generators
Mathematics of Computation
Low-Complexity Bit-Parallel Canonical and Normal Basis Multipliers for a Class of Finite Fields
IEEE Transactions on Computers
Low Complexity Bit-Parallel Multipliers for a Class of Finite Fields
IEEE Transactions on Computers
IEEE Transactions on Computers
A New Construction of Massey-Omura Parallel Multiplier over GF(2^{m})
IEEE Transactions on Computers
A Modified Massey-Omura Parallel Multiplier for a Class of Finite Fields
IEEE Transactions on Computers
Finite Field Multiplier Using Redundant Representation
IEEE Transactions on Computers
Symmetry and Duality in Normal Basis Multiplication
AAECC-6 Proceedings of the 6th International Conference, on Applied Algebra, Algebraic Algorithms and Error-Correcting Codes
Gauss Periods and Fast Exponentiation in Finite Fields (Extended Abstract)
LATIN '95 Proceedings of the Second Latin American Symposium on Theoretical Informatics
Fast Multiplication in Finite Fields GF(2N)
CHES '99 Proceedings of the First International Workshop on Cryptographic Hardware and Embedded Systems
Efficient Multiplication Beyond Optimal Normal Bases
IEEE Transactions on Computers
A Redundant Representation of GF(q^n) for Designing Arithmetic Circuits
IEEE Transactions on Computers
Guide to Elliptic Curve Cryptography
Guide to Elliptic Curve Cryptography
Low Complexity Word-Level Sequential Normal Basis Multipliers
IEEE Transactions on Computers
Comb Architectures for Finite Field Multiplication in F(2^m)
IEEE Transactions on Computers
A New Finite-Field Multiplier Using Redundant Representation
IEEE Transactions on Computers
A bit-serial word-parallel finite field multiplier using redundant basis in F2M
AsiaCSN '07 Proceedings of the Fourth IASTED Asian Conference on Communication Systems and Networks
GF(2m) finite-field multipliers with reduced activity variations
WAIFI'12 Proceedings of the 4th international conference on Arithmetic of Finite Fields
Information Processing Letters
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In this paper, a high-speed word level finite field multiplier in F2m using redundant representation is proposed. For the class of fields that there exists a type I optimal normal basis, the new architecture has significantly higher speed compared to previously proposed architectures using either normal basis or redundant representation at the expense of moderately higher area complexity. One of the unique features of the proposed multiplier is that the critical path delay is not a function of the field size nor the word size. It is shown that the new multiplier outperforms all the other multipliers in comparison when considering the product of area and delay as a measure of performance. VLSI implementation of the proposed multiplier in a 0.18-µm complimentary metal-oxide-semiconductor (CMOS) process is also presented.