A bit-serial word-parallel finite field multiplier using redundant basis in F2M

Authors:
Ashkan Hosseinzadeh Namin;Huapeng Wu;Majid Ahmadi
Affiliations:
University of Windsor, Windsor, Ontario, Canada;University of Windsor, Windsor, Ontario, Canada;University of Windsor, Windsor, Ontario, Canada
Venue:
AsiaCSN '07 Proceedings of the Fourth IASTED Asian Conference on Communication Systems and Networks
Year:
2007

Citing 5
Cited 1

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Abstract

A high speed bit-serial word-parallel finite field multiplier using redundant basis is proposed. It has been shown that the proposed architecture has higher speed compared to the previously proposed hybrid architectures using the same basis while having moderate complexity. The hybrid architecture of the proposed design provides designer the ability to set the trade off between area and delay during the design process.