Introduction to finite fields and their applications
Introduction to finite fields and their applications
Optimal normal bases in GF(pn)
Discrete Applied Mathematics
Low-Complexity Bit-Parallel Canonical and Normal Basis Multipliers for a Class of Finite Fields
IEEE Transactions on Computers
New Low-Complexity Bit-Parallel Finite Field Multipliers Using Weakly Dual Bases
IEEE Transactions on Computers
New Systolic Arrays for C + AB2, Inversion, and Division in GF(2m)
IEEE Transactions on Computers
An Efficient Optimal Normal Basis Type II Multiplier
IEEE Transactions on Computers
IEEE Transactions on Computers
Cryptography and Secure Communications
Cryptography and Secure Communications
Handbook of Applied Cryptography
Handbook of Applied Cryptography
A New Construction of Massey-Omura Parallel Multiplier over GF(2^{m})
IEEE Transactions on Computers
GF(2m) Multiplication and Division Over the Dual Basis
IEEE Transactions on Computers
A Search of Minimal Key Functions for Normal Basis Multipliers
IEEE Transactions on Computers
VLSI Designs for Multiplication over Finite Fields GF (2m)
AAECC-6 Proceedings of the 6th International Conference, on Applied Algebra, Algebraic Algorithms and Error-Correcting Codes
ARITH '03 Proceedings of the 16th IEEE Symposium on Computer Arithmetic (ARITH-16'03)
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Systolic Multipliers for Finite Fields GF(2m)
IEEE Transactions on Computers
Low-complexity multiplier for GF(2m) based on all-one polynomials
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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A new bit-parallel systolic multiplier over GF(2m) under the polynomial basis and normal basis is proposed. This new circuit is constructed by m 2 identical cells, each of which consists of one two-input AND gate, one three-input XOR gate and five 1-bit latches. Especially, the proposed architecture is without the basis conversion as compared to the well-known multipliers with the redundant representation. With this proposed multiplier, a parallel-in parallel-out systolic array has also been developed for computing inversion and division over GF(2m). The proposed architectures are well suited to VLSI systems due to their regular interconnection pattern and modular structure.