Ringed bit-parallel systolic multipliers over a class of fields GF(2m)

Authors:
Yeun-Renn Ting;Erl-Huei Lu;Ya-Cheng Lu
Affiliations:
The Department of Electrical Engineering, Chang Gung University, 259 Wen-Hwa 1st Road, Kwei-San, Tao-Yuan, Taiwan 333, ROC;The Department of Electrical Engineering, Chang Gung University, 259 Wen-Hwa 1st Road, Kwei-San, Tao-Yuan, Taiwan 333, ROC;The Department of Electrical Engineering, Chang Gung University, 259 Wen-Hwa 1st Road, Kwei-San, Tao-Yuan, Taiwan 333, ROC
Venue:
Integration, the VLSI Journal
Year:
2005

Citing 7
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Abstract

This paper presents ringed bit-parallel systolic multipliers for computing AB+C over a class of finite fields GF(2m), in which all elements are represented using a root of an all-one polynomial or an equally spaced polynomial. Compared to other related multipliers, the proposed multipliers reveal properties of lower hardware complexity, lower latency and free of global connection. Furthermore, we proposed a general rule to plan the multipliers. This rule makes the planning easy.