Introduction to finite fields and their applications
Introduction to finite fields and their applications
Structure of parallel multipliers for a class of fields GF(2m)
Information and Computation
Montgomery Multiplication in GF(2^k
Designs, Codes and Cryptography
New Low-Complexity Bit-Parallel Finite Field Multipliers Using Weakly Dual Bases
IEEE Transactions on Computers
IEEE Transactions on Computers
Linear System Theory and Design
Linear System Theory and Design
A Scalable Architecture for Modular Multiplication Based on Montgomery's Algorithm
IEEE Transactions on Computers
Primitive Polynomials Over GF(2) of Degree up to 660 with Uniformly Distributed Coefficients
Journal of Electronic Testing: Theory and Applications
Efficient scalable VLSI architecture for Montgomery inversion in GF(p)
Integration, the VLSI Journal
Low-Complexity Bit-Parallel Systolic Montgomery Multipliers for Special Classes of GF(2^m)
IEEE Transactions on Computers
A digit-serial multiplier for finite field GF(2m)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Optimum Digit Serial GF(2^m) Multipliers for Curve-Based Cryptography
IEEE Transactions on Computers
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Unified parallel systolic multiplier over GF(2m)
Journal of Computer Science and Technology
CMOS Digital Integrated Circuits Analysis & Design
CMOS Digital Integrated Circuits Analysis & Design
Low complexity digit serial systolic montgomery multipliers for special class of GF(2m)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This work presents a novel scalable and systolic Montgomery's algorithm in GF(2m). The proposed algorithm is based on the Toeplitz matrix-vector representation, which obtains the scalable and systolic Montgomery multiplier in a flexible manner, and can adapt to the required precision. Analytical results indicate that the proposed multiplier over the generic field of GF(2m) has a latency of d + n(2n + 1), where n = ⌈m/d⌉, and d denotes the selected digital size. The latency is reduced to d + n(n + 1) clock cycles when the field is constructed from generalized equally-spaced polynomials. Since the selected digital size is d ≥ 5 bits, the proposed architectures have lower time-space complexity than traditional digit-serial multipliers. Moreover, the proposed architectures have regularity, modularity and local interconnect ability, making them very suitable for VLSI implementation.