Self-checking and fault-tolerant digital design
Self-checking and fault-tolerant digital design
Carry checking/parity prediction adders and ALUs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on system-level interconnect prediction (SLIP)
Designing a Radiation Hardened 8051-Like Micro-Controller
SBCCI '00 Proceedings of the 13th symposium on Integrated circuits and systems design
Proceedings of the 15th symposium on Integrated circuits and systems design
Highly fault-tolerant parallel computation
FOCS '96 Proceedings of the 37th Annual Symposium on Foundations of Computer Science
Evaluating One-Hot Encoding Finite State Machines for SEU Reliability in SRAM-based FPGAs
IOLTS '06 Proceedings of the 12th IEEE International Symposium on On-Line Testing
A memory soft error measurement on production systems
ATC'07 2007 USENIX Annual Technical Conference on Proceedings of the USENIX Annual Technical Conference
Low complexity bit parallel architectures for polynomial basis multiplication over GF(2m)
IEEE Transactions on Computers
| Hi-index | 0.00 |
This paper presents a new method for fault-tolerant computing where for a given error rate, r, the hamming distance between correct inputs and faulty inputs, as well as the hamming distance between correct results and faulty results, is preserved throughout processing; thereby enabling correction of up to r transient faults per computation cycle. The new method is compared and contrasted with current protection methods and its cost/performance is analyzed.