VLSI performance evaluation and analysis of systolic and semisystolic finite field multipliers

Authors:
Ravi Kumar Satzoda;Chip-Hong Chang
Affiliations:
Centre for High Performance Embedded Systems, Nanyang Technological University, Singapore;Centre for High Performance Embedded Systems, Nanyang Technological University, Singapore
Venue:
ACSAC'05 Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture
Year:
2005

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Abstract

Finite field multiplication in GF(2m) is an ineluctable operation in elliptic curve cryptography. The objective of this paper is to survey fast and efficient hardware implementations of systolic and semisystolic finite field multipliers in GF(2m) with two algorithmic schemes – LSB-first and MSB-first. These algorithms have been mapped to seven variants of recently proposed array-type finite-field multiplier implementations with different input-output configurations. The relative VLSI performance merits of these ASIC prototypes with respect to their field orders are evaluated and compared under uniform constraints and in properly defined simulation runs on a Synopsys environment using the TSMC 0.18μm CMOS standard cell library. The results of the simulation provide an insight into the behavior of various configurations of array-type finite-field multiplier so that system architect can use them to determine the most appropriate finite field multiplier topology for required design features.