An optimized design for serial-parallel finite field multiplication over GF(2m) based on all-one polynomials

Authors:
P. K. Meher;Yajun Ha;Chiou-Yng Lee
Affiliations:
Nanyang Technological University, Singapore;National University of Singapore, Singapore;Lunghwa University, Taiwan
Venue:
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Year:
2009

Citing 11
Cited 2

Introduction to finite fields and their applications

Introduction to finite fields and their applications
VLSI array processors

VLSI array processors
A Comparison of VLSI Architecture of Finite Field Multipliers Using Dual, Normal, or Standard Bases

IEEE Transactions on Computers
Structure of parallel multipliers for a class of fields GF(2m)

Information and Computation
Modular Construction of Low Complexity Parallel Multipliers for a Class of Finite Fields GF(2/sup m/)

IEEE Transactions on Computers - Special issue on computer arithmetic
Low-Complexity Bit-Parallel Canonical and Normal Basis Multipliers for a Class of Finite Fields

IEEE Transactions on Computers
Low Complexity Bit-Parallel Multipliers for a Class of Finite Fields

IEEE Transactions on Computers
Bit-Parallel Systolic Multipliers for GF(2m) Fields Defined by All-One and Equally Spaced Polynomials

IEEE Transactions on Computers
Low-Complexity Bit-Parallel Systolic Montgomery Multipliers for Special Classes of GF(2^m)

IEEE Transactions on Computers
Low Complexity Bit-Parallel Multiplier for GF(2^m) Defined by All-One Polynomials Using Redundant Representation

IEEE Transactions on Computers
On efficient implementation of accumulation in finite field over GF(2m) and its applications

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Low-complexity multiplier for GF(2m) based on all-one polynomials

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Novel bit-parallel multiplier for GF(2m) defined by all-one polynomial using generalized Karatsuba algorithm

Information Processing Letters

Quantified Score

Hi-index	0.00

Visualization

Abstract

In this paper, we derive a recursive algorithm for finite field multiplication over GF(2m) based on irreducible all-one-polynomials (AOP), where the modular reduction of degree is achieved by cyclic-left-shift without any logic operations. A regular and localized bit-level dependence graph (DG) is derived from the proposed algorithm and mapped into an array architecture, where the modular reduction is achieved by a serial-in parallel-out shift-register. The multiplier is optimized further to perform the accumulation of partial products by the T flip flops of the output register without XOR gates. It is interesting to note that the optimized structure consists of an array of (m+1) AND gates between an array of (m+1) D flip flops and an array of (m+1) T flip flops. The proposed structure therefore involves significantly less area and less computation time compared with the corresponding existing structures.