Low latency systolic montgomery multiplier for finite field GF(2m) based on pentanomials

Authors:
Jiafeng Xie;Jian Jun He;Pramod Kumar Meher
Affiliations:
School of Information Science and Engineering, Central South University, Changsha, Hunan, China;School of Information Science and Engineering, Central South University, Changsha, Hunan, China;Department of Embedded Systems, Institute for Infocomm Research, Singapore
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2013

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Abstract

In this paper, we present a low latency systolic Montgomery multiplier over GF(2m) based on irreducible pentanomials. An efficient algorithm is presented to decompose the multiplication into a number of independent units to facilitate parallel processing. Besides, a novel so-called "pre-computed addition" technique is introduced to further reduce the latency. The proposed design involves significantly less area-delay and power-delay complexities compared with the best of the existing designs. It has the same or shorter critical-path and involves nearly one-fourth of the latency of the other in case of the National Institute of Standards and Technology recommended irreducible pentanomials.