Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Variability driven gate sizing for binning yield optimization
Proceedings of the 43rd annual Design Automation Conference
Dynamic thermal clock skew compensation using tunable delay buffers
Proceedings of the 2006 international symposium on Low power electronics and design
Design for Manufacturability and Statistical Design: A Comprehensive Approach
Design for Manufacturability and Statistical Design: A Comprehensive Approach
A self-adjusting clock tree architecture to cope with temperature variations
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Statistical timing yield optimization by gate sizing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Novel Delay Fault Testing Methodology Using Low-Overhead Built-In Delay Sensor
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficiently tolerating timing violations in pipelined microprocessors
Proceedings of the 50th Annual Design Automation Conference
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We propose a self-adjusting pipeline structure to enhance chip performance and robustness considering the effects of process variations. We achieve this by introducing delay sensors to monitor internal timing violations within a pipeline stage and variable clock skew buffers to adjust the timing of the pipeline stage based on the feedback from the delay sensors. Furthermore, we formulate the delay sensor insertion and variable clock skew configuration problem as a stochastic mixed-integer programming problem and propose a simulated-annealing based algorithm to solve it. A comparison between the designs with and without the self-adjusting enhancement reveals that, we are able to improve the average performance of a batch of chips by 9.5%.