Efficiently tolerating timing violations in pipelined microprocessors

  • Authors:
  • Koushik Chakraborty;Brennan Cozzens;Sanghamitra Roy;Dean M. Ancajas

  • Affiliations:
  • Utah State University;Utah State University;Utah State University;Utah State University

  • Venue:
  • Proceedings of the 50th Annual Design Automation Conference
  • Year:
  • 2013

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Abstract

Early prediction of an upcoming timing violation presents a tremendous opportunity to mask the performance overhead of tolerating these faults. In this paper, we explore several techniques for optimizing instruction scheduling in an Out-of-Order pipeline, exploiting this new perspective in robust system design. Compared to recently proposed stall based techniques for tolerating predictable timing violations, we demonstrate a massive reduction in performance overhead, while supporting correct execution in faulty environments (64--97% across different benchmarks).