VLSI Architectures for Computing Multiplications and Inverses in GF(2m)
IEEE Transactions on Computers
Architecture of the PSC-a programmable systolic chip
ISCA '83 Proceedings of the 10th annual international symposium on Computer architecture
VLSI architecture of modified Euclidean algorithm for Reed-Solomon code
Information Sciences: an International Journal
Reconfigurable adaptive FEC system with interleaving
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
A self-adjusting clock tree architecture to cope with temperature variations
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
SACTA: a self-adjusting clock tree architecture for adapting to thermal-induced delay variation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This brief contribution proposes a new class of systolic-arrays to perform Binary Reed-Solomon (RS) decoding procedures including erasure correction. Such RS decoder is suitable for VLSI implementation since the arrays consist of simple processing elements of the same type