Body bias generator for leakage power reduction of low-voltage digital logic circuits

Authors:
Ji-Yong Jeong;Gil-Su Kim;Jong-Pil Son;Woo-Jin Rim;Soo-Won Kim
Affiliations:
ASIC Design Lab., Dept. of Electronics Eng., Korea University, Seoul, Korea;ASIC Design Lab., Dept. of Electronics Eng., Korea University, Seoul, Korea;ASIC Design Lab., Dept. of Electronics Eng., Korea University, Seoul, Korea;ASIC Design Lab., Dept. of Electronics Eng., Korea University, Seoul, Korea;ASIC Design Lab., Dept. of Electronics Eng., Korea University, Seoul, Korea
Venue:
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Year:
2006

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Abstract

This paper proposes body-bias generator for leakage power reduction of digital logic circuits which operates at low supply voltage of 0.5V. The proposed circuit adopts double charge pumping scheme to enhance the pumping gain. The proposed circuit is fabricated using 0.13 μm CMOS process and measurement result demonstrates stable operation with body-bias voltage of -0.95V. We apply the proposed circuit to 64-bit carry look-ahead adder to demonstrate its performance. We report that the leakage power of 64-bit carry look-ahead adder can dramatically be reduced by adopting proposed substratebias generator. The estimated leakage power reduction is 90% (T=75°C).