Characterizing and modeling minimum energy operation for subthreshold circuits
Proceedings of the 2004 international symposium on Low power electronics and design
Energy optimality and variability in subthreshold design
Proceedings of the 2006 international symposium on Low power electronics and design
Analysis and optimization of sleep modes in subthreshold circuit design
Proceedings of the 44th annual Design Automation Conference
Nanometer MOSFET effects on the minimum-energy point of 45nm subthreshold logic
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Interests and limitations of technology scaling for subthreshold logic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The gm/ID Methodology, a sizing tool for low-voltage analog CMOS Circuits: The semi-empirical and compact model approaches
Hi-index | 0.00 |
Sub-threshold operation is an efficient solution for ultra low power applications. However, it is very sensitive to process variability which can impact the robustness and effective performance of the circuit. On the other hand this sensitivity decreases as we move towards near-threshold operation. n this paper, the impact of variability on sub-threshold and nearthreshold circuit performance is investigated through analytical modeling and circuit simulation in a 65 nm industrial low power CMOS process.We show that variability moves the effective minimum energy point towards the near threshold region. Thus, we demonstrate that when variability is taken into account, a complete model that includes the near threshold (moderate inversion) region is necessary in order to correctly model circuit performance around the minimum energy point. Finally, we present the resulting speed-consumption trade-off in a variability-aware analysis of sub-threshold and near-threshold operation.