Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Design of High-Performance Microprocessor Circuits
Design of High-Performance Microprocessor Circuits
Operation and Modeling of the Mos Transistor (The Oxford Series in Electrical and Computer Engineering)
Theoretical and practical limits of dynamic voltage scaling
Proceedings of the 41st annual Design Automation Conference
Characterizing and modeling minimum energy operation for subthreshold circuits
Proceedings of the 2004 international symposium on Low power electronics and design
Sub-threshold Design for Ultra Low-Power Systems (Series on Integrated Circuits and Systems)
Sub-threshold Design for Ultra Low-Power Systems (Series on Integrated Circuits and Systems)
Digital Signal Processing (4th Edition)
Digital Signal Processing (4th Edition)
Energy-efficient subthreshold processor design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper develops and demonstrates the design and optimization method for fixed coefficient Finite Impulse Response (FIR) filters using sub-threshold circuits to achieve the minimum energy per operation. Sub-threshold circuit current, delay, power consumption, energy per operation and temperature dependence are modeled theoretically and analyzed using Matlab. Then the filter design and optimization are presented. With a frequency characteristic of 80 dB magnitude and 9.6 kHz bandwidth, the 16-bit fixed-point coefficients of the linear phase equiripple low-pass filter are generated from Matlab. Canonical Signed Digit (CSD) arithmetic is used for multiplierless design to improve both cost and performance. The transposed structure and symmetry structure are applied to optimize the delay and cost further. Horner's rule is used to improve the precision. Tree-height reduction and subexpression sharing at Register Transfer Level (RTL) are used for further delay and cost reduction. Six versions of the filter with the same group of coefficients are designed and synthesized using Design Compiler with a 65 nm process. Synthesis results show that the area of the final version is reduced by 44% compared with the original design at a fixed frequency of 250 MHz, and at the highest frequency of each design, the area is reduce by about 23% while the performance is improved by 60%. These results show the design and optimization method developed in this paper can improve both the area and performance significantly. One adder from the synthesis netlist is simulated at the transistor-level using HSPICE to obtain characteristics of sub-threshold operations. The supply voltage varies from 1.2 to 0.08 V and temperatures from 0 to 110°C. The experiment results verify most characteristics of the sub-threshold models, but also reveal some limitations and defects of the theoretical models and previous results. The observations are discussed carefully with quantitative and qualitative analysis. For 25°C, the minimum energy point for the adder is 0.22 V. Finally, the results of the adder are used to estimate the energy per operation for the filters. For a fixed frequency of 36.4 kHz at 0.22 V, the estimated energy values vary from 4.8 to about 2.7 pJ for the six designed filters.