Operation and modeling of the MOS transistor
Operation and modeling of the MOS transistor
Parameter variations and impact on circuits and microarchitecture
Proceedings of the 40th annual Design Automation Conference
Optimal Voltages and Sizing for Low Power
VLSID '99 Proceedings of the 12th International Conference on VLSI Design - 'VLSI for the Information Appliance'
Temperature-adaptive voltage tuning for enhanced energy efficiency in ultra-low-voltage circuits
Microelectronics Journal
Temperature-adaptive voltage scaling for enhanced energy efficiency in subthreshold memory arrays
Microelectronics Journal
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Operating an integrated circuit at the prescribed nominal supply voltage is not preferable for reliable circuit operation under temperature fluctuations. A design methodology based on optimizing the supply voltage for temperature variation insensitive circuit performance is presented in this paper. Circuits display temperature variation insensitive delay characteristics when operated at a supply voltage 45% to 53% lower than the nominal supply voltage (VDD = 1.8V) in a 180nm CMOS technology. Integrated circuits operating at scaled supply voltages consume low power at the cost of reduced speed. The proposed design methodology of optimizing the supply voltage for temperature variation insensitive circuit performance is, therefore, particularly attractive in low power applications with relaxed speed requirements. The energy, delay, and energy-delay product (EDP) are compared at the supply voltages that yield temperature variation insensitive circuit performance and minimum energy-delay product. Results indicate that low-power integrated circuits can also be made insensitive to temperature fluctuations with a modest amount of increase in energy-delay product.