Wattch: a framework for architectural-level power analysis and optimizations
Proceedings of the 27th annual international symposium on Computer architecture
Power efficiency of voltage scaling in multiple clock, multiple voltage cores
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Dynamic frequency and voltage control for a multiple clock domain microarchitecture
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
A critical analysis of application-adaptive multiple clock processors
Proceedings of the 2003 international symposium on Low power electronics and design
Design and reliability challenges in nanometer technologies
Proceedings of the 41st annual Design Automation Conference
Proceedings of the 41st annual Design Automation Conference
Considering process variations during system-level power analysis
Proceedings of the 2006 international symposium on Low power electronics and design
Impact of Process and Temperature Variations on Network-on-Chip Design Exploration
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Variation-tolerant dynamic power management at the system-level
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Variation-aware system-level power analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The authors present microarchitecture-level statistical models for characterizing process and system parameter variability, concentrating on gate length and on-chip temperature variations. To assess the effect of microarchitecture decisions on these variations, and vice versa, they propose a joint performance, power, and variability metric that distinguishes among various design choices.