Low-power circuits using dynamic threshold devices

  • Authors:
  • Paul Beckett

  • Affiliations:
  • RMIT University

  • Venue:
  • GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
  • Year:
  • 2005

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Abstract

We present simulations for ultra-thin body, fully-depleted, double-gate (DG) silicon-on-insulator (SOI) devices that can be readily optimized for both static power loss and performance by dynamically shifting the threshold voltage during operation. A small number of simple circuits are analyzed and it is demonstrated that subthreshold power can be reduced by a factor in excess of 103 for these examples.