A symbolic method to reduce power consumption of circuits containing false paths

Authors:
R. Iris Bahar;Gary D. Hachtel;Enrico Macii;Fabio Somenzi
Affiliations:
University of Colorado, Department of Electrical and Computer Engineering, Boulder, CO;University of Colorado, Department of Electrical and Computer Engineering, Boulder, CO;University of Colorado, Department of Electrical and Computer Engineering, Boulder, CO and Politecnico di Torino, Dipartimento di Automatica e Informatica, Torino, ITALY;University of Colorado, Department of Electrical and Computer Engineering, Boulder, CO
Venue:
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Year:
1994

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Abstract

Power dissipation in technology mapped circuits can be reduced by performing gate re-sizing. Recently we have proposed a symbolic procedure which exploits the compactness of the ADD data structure to accurately calculate the arrival times at each node of a circuit for any primary input vector. In this paper we extend our timing analysis tool to the symbolic calculation of required times and slacks, and we use this information to identify gates of the circuits that can be re-sized. The nice feature of our approach is that it takes into account the presence of false paths naturally. As shown by the experimental results, circuits re-synthesized with the technique we present in this paper are guaranteed to be at least as fast as the original implementations, but smaller and substantially less power-consuming.