Power reduction by simultaneous voltage scaling and gate sizing
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Physical design with multiple on-chip voltages
Proceedings of the 2002 international symposium on Physical design
On gate level power optimization using dual-supply voltages
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Potential slack: an effective metric of combinational circuit performance
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2003 international symposium on Low power electronics and design
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We present an approach for applying two supply voltages to optimize power in CMOS digital circuits under the timing constraints. Given a technology-mapped network, we first analyze the timing slack distribution and power/delay model within the circuit. The power reduction is then translated into the Maximal-Weighted-Independent-Set (MWIS) problem. We develop an effective power optimization algorithm based on MWIS. To reduce the possible power penalty of level converters (LCs) at the interface of two supply voltages, we use a "constrained" F-M algorithm to minimize the number of LCs. Experimental results show that the total power saving up to 35% (average of about 19%) is achieved without degrading the circuit performance. The power-delay tradeoff is provided by specifying different timing constraints for power optimization.