A quick method for energy optimized gate sizing of digital circuits

Authors:
Mustafa Aktan;Dursun Baran;Vojin G. Oklobdzija
Affiliations:
Department of Electrical and Computer Eng., New Mexico State University, NM;Department of Electrical Eng., University of Texas at Dallas, TX;Department of Electrical and Computer Eng., New Mexico State University, NM
Venue:
PATMOS'11 Proceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation
Year:
2011

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Abstract

Exploration of energy & delay trade-offs requires a sizing solution for minimal energy under operating delay and output load constraints. In this work, a simple method called Constant Stage Effort Ratio (CSER) is proposed for minimal energy solution of digital circuits with a given target delay. The proposed method has a linear run-time dependence on the number of logic gates that is exponential for the optimal solution. As sample cases, the proposed algorithm is applied to parallel VLSI adders with varying bit-widths at 65nm CMOS technology. CSER sizing algorithm provides more than 300× run-time improvement compared to energy optimal solution with a worst case difference of 10% in energy for a 128-bits Kogge-Stone adder.