2nd order adiabatic computation with 2N-2P and 2N-2N2P logic circuits
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Single-phase source-coupled adiabatic logic
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Clocked CMOS adiabatic logic with integrated single-phase power-clock supply
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A true single-phase 8-bit adiabatic multiplier
Proceedings of the 38th annual Design Automation Conference
Energy recovering static memory
Proceedings of the 2002 international symposium on Low power electronics and design
A 225 MHz resonant clocked ASIC chip
Proceedings of the 2003 international symposium on Low power electronics and design
Asymptotically zero energy computing using split-level charge recovery logic
Asymptotically zero energy computing using split-level charge recovery logic
Reversibility for efficient computing
Reversibility for efficient computing
Reversible computer engineering and architecture
Reversible computer engineering and architecture
A true single-phase energy-recovery multiplier
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Recent advances in CMOS VLSI design have taken us to real working chips that rely on controlled charge recovery to operate at sub-stantially lower power dissipation levels than their conventional counterparts. In this paper, we present two such chips that were designed in our research group and highlight some of the promising charge-recovery techniques in practice. Although their origins can be traced back to the early adiabatic circuits, these techniques approach energy recycling from a more practical angle, shedding reversibility to achieve operating frequencies in excess of 1GHz with relatively low overheads