On the compact designs of low power reversible decoders and sequential circuits

Authors:
Lafifa Jamal;Md. Masbaul Alam Polash;M. A. Mottalib;Hafiz Md. Hasan Babu
Affiliations:
Dept. of Computer Science and Engineering, University of Dhaka, Dhaka, Bangladesh;Dept. of Computer Science and Engineering, University of Dhaka, Dhaka, Bangladesh;Dept. of CIT, Islamic University of Technology, Gazipur, Bangladesh;Dept. of Computer Science and Engineering, University of Dhaka, Dhaka, Bangladesh
Venue:
VDAT'12 Proceedings of the 16th international conference on Progress in VLSI Design and Test
Year:
2012

Citing 7
Cited 0

Reversible Logic Synthesis for Minimization of Full-Adder Circuit

DSD '03 Proceedings of the Euromicro Symposium on Digital Systems Design
Synthesis of Full-Adder Circuit Using Reversible Logic

VLSID '04 Proceedings of the 17th International Conference on VLSI Design
Design of a compact reversible binary coded decimal adder circuit

Journal of Systems Architecture: the EUROMICRO Journal
Efficient approaches for designing reversible Binary Coded Decimal adders

Microelectronics Journal
Irreversibility and heat generation in the computing process

IBM Journal of Research and Development
Logical reversibility of computation

IBM Journal of Research and Development
Design of Reversible Latches Optimized for Quantum Cost, Delay and Garbage Outputs

VLSID '10 Proceedings of the 2010 23rd International Conference on VLSI Design

Quantified Score

Hi-index	0.00

Visualization

Abstract

Conventional logic dissipates more power by losing bits of information whereas reversibility recovers bit loss from the unique input-output mapping. Reversible Computation has high promise oflow power consumption. In this paper, we have proposed a new 4x4 reversible gate (namely BJ gate) which is used to design reversible J-K flip-flop. We have also proposed the design of low power reversible decoders, reversible sequence counter and reversible instruction register. These circuits are analyzed with the existing ones. The comparative results show that the proposed designs of reversible decoders and sequential circuits outperform the existing designs in terms of numbers of gates, garbage outputs and quantum cost. Some lower bounds on the number of gates and garbage outputs of the proposed decoder circuits have also been proposed.