Reversible Logic Synthesis for Minimization of Full-Adder Circuit

Authors:
Hafiz Hasan Babu;Rafiqul Islam;Ahsan Raja Chowdhury;Syed Mostahed Ali Chowdhury
Affiliations:
-;-;-;-
Venue:
DSD '03 Proceedings of the Euromicro Symposium on Digital Systems Design
Year:
2003

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Abstract

Reversible logic is of the growing importance to manyfuture technologies. A reversible circuit maps eachoutput vector, into a unique input vector, and vice versa.This paper introduces an approach to synthesis thegeneralized multi-rail reversible cascades withminimizing the "garbage bit" and number of reversiblegates, which is the main challenge of reversible logicsynthesis. This proposed full-adder circuit contains onlythree gates and two garbage outputs whereas earlierfull-adder circuit [10,13] requires four gates andproduces two garbage outputs and another existing full-addercircuit [6] requires three gates but produces threegarbage outputs. Thus, the proposed full-adder circuit isefficient in terms of number of gates with compared to[10,13] as well as in terms of number of garbage outputswith compared to [6].