Quantum computation and quantum information
Quantum computation and quantum information
Efficient Adder Circuits Based on a Conservative Reversible Logic Gate
ISVLSI '02 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
Reversible Logic Synthesis for Minimization of Full-Adder Circuit
DSD '03 Proceedings of the Euromicro Symposium on Digital Systems Design
Synthesis of Full-Adder Circuit Using Reversible Logic
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
Online Testable Reversible Logic Circuit Design using NAND Blocks
DFT '04 Proceedings of the Defect and Fault Tolerance in VLSI Systems, 19th IEEE International Symposium
Design of a Reversible Binary Coded Decimal Adder by Using Reversible 4-Bit Parallel Adder
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
Irreversibility and heat generation in the computing process
IBM Journal of Research and Development
Logical reversibility of computation
IBM Journal of Research and Development
Efficient approaches for designing reversible Binary Coded Decimal adders
Microelectronics Journal
Efficient Reversible Logic Design of BCD Subtractors
Transactions on Computational Science III
Transistor realization of reversible "ZS" series gates and reversible array multiplier
Microelectronics Journal
Novel design of a fast reversible Wallace sign multiplier circuit in nanotechnology
Microelectronics Journal
The new BCD subtractor and its reversible logic implementation
ACSAC'06 Proceedings of the 11th Asia-Pacific conference on Advances in Computer Systems Architecture
Ultra-area-efficient reversible multiplier
Microelectronics Journal
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Reversible logic is emerging as a promising area of research having its applications in quantum computing, nanotechnology, and optical computing. The classical set of gates such as AND, OR, and EXOR are not reversible. In this paper, a new 4 *4 reversible gate called “TSG” gate is proposed and is used to design efficient adder units. The proposed gate is used to design ripple carry adder, BCD adder and the carry look-ahead adder. The most significant aspect of the proposed gate is that it can work singly as a reversible full adder i.e reversible full adder can now be implemented with a single gate only. It is demonstrated that the adder architectures using the proposed gate are much better and optimized, compared to their counterparts existing in literature, both in terms of number of reversible gates and the garbage outputs.