Transistor realization of reversible "ZS" series gates and reversible array multiplier

  • Authors:

  • Rigui Zhou;Yang Shi;Hui'An Wang;Jian Cao

  • Affiliations:

  • College of Information Engineering, East China Jiao Tong University, Nanchang, Jiangxi 330013, China and Department of Electronics, Carleton University, Ottawa, Ontario, Canada K1S 5B6 and Key Lab ...;College of Information Engineering, East China Jiao Tong University, Nanchang, Jiangxi 330013, China;College of Information Engineering, East China Jiao Tong University, Nanchang, Jiangxi 330013, China;College of Information Engineering, East China Jiao Tong University, Nanchang, Jiangxi 330013, China

  • Venue:
  • Microelectronics Journal
  • Year:
  • 2011

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Abstract

In order to reduce the redundant Toffoli gates and the line-crossings in the classical reversible full adder appearing in the present literatures, this paper gives a reconstructive structure of Fredkin gate, called RF gate, the corresponding quantum equivalent realization and electronic circuitry construction based on CMOS technology and pass-transistor of this gate are also designed in this paper. With the assistance of the RF gate and the basic reversible gates (including NOT gate, CNOT gate and Toffoli gate), we design new 4x4 reversible gates called ''ZS'' series gates and its corresponding electronic circuitry construction. The proposed ''ZS'' series gates have the ability to operate reversible add operation between two signed numbers by a single gate and at lower power consumption. At the same time, as an application of ''ZS'' series gates, this paper also designs reversible array multiplier in order to achieve the signed multiplication. It can be theoretically proved that the proposed reversible array multiplier can eliminate power loss associated with the irreversible operation of classical computer, and will be exponentially lower than reversible parallel multiplier with respect to time complexity.