Online Testable Reversible Logic Circuit Design using NAND Blocks

Authors:
D. P. Vasudevan;P. K. Lala;J. P. Parkerson
Affiliations:
University of Arkansas, Fayetteville;University of Arkansas, Fayetteville;University of Arkansas, Fayetteville
Venue:
DFT '04 Proceedings of the Defect and Fault Tolerance in VLSI Systems, 19th IEEE International Symposium
Year:
2004

Citing 0
Cited 2

CMOS Realization of Online Testable Reversible Logic Gates

ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
A novel reversible TSG gate and its application for designing reversible carry look-ahead and other adder architectures

ACSAC'05 Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture

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Abstract

A technique for on-line testable reversible logic circuit is presented. Three new reversible logic gates have been introduced in this paper. These gates can be used to implement reversible digital circuits of various levels of complexity. The major feature of these gates is that they provide online testability for circuits implemented using them. The application of these gates in implementation of a subset of MCNC benchmark circuits is provided.