CMOS Realization of Online Testable Reversible Logic Gates

Authors:
D. P. Vasudevan;P. K. Lala;J. P. Parkerson
Affiliations:
University of Arkansas;University of Arkansas;University of Arkansas
Venue:
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
Year:
2005

Citing 3
Cited 0

Online Testable Reversible Logic Circuit Design using NAND Blocks

DFT '04 Proceedings of the Defect and Fault Tolerance in VLSI Systems, 19th IEEE International Symposium
Irreversibility and heat generation in the computing process

IBM Journal of Research and Development
Logical reversibility of computation

IBM Journal of Research and Development

Quantified Score

Hi-index	0.00

Visualization

Abstract

Three reversible logic gates that can be used to implement reversible digital circuits with various levels of complexity are proposed. The major feature of these gates is that they provide online-testability for circuits implemented using them. The CMOS realization of these gates is presented in this paper.